l   Standards

n   GB/T20851-2019 compatible

n   AEC-Q100 grade 2 (-40⁰C to +105⁰C)

l   CPU Core: ARM Cortex M0 (32-bit CPU)

n   From 500KHz up to 45MHz max

n   0.95DMIPS/MHz

n   0.5KB high speed cache

l   5.8GHz DSRC processor

n   GB/T20851.2-2019 compatible

n   3.5μA RF wakeup@-50dBm

n   5.5μA IF wakeup@20μV, -63dBm

n   10μA period wakeup@-85dBm@2s

n   -80dBm RX sensitivity

n   6dBm max TX power

n   Support TX PN9 and 14KHz square wave

l   Ultra-low-power

n   2.0V to 3.6V power supply

n   0.23μA @ Power down mode with 20.8μs wakeup time from flash

n   0.83μA @ Deep sleep mode (all SRAM retention) with 11.9μs wakeup time from flash

l   Clock sources

n   45MHz max RC oscillator

n   16.384/32.768MHz XTAL for DSRC

n   32KHz Crystal oscillator or RC oscillator for WDT or RTC

n   40MHz clock for CAN controller

l   Debug support

n   Serial wire debug (SWD) support

l   Memories

n   Up to 256KB Flash memory

n   32KB SRAM

n   128B always-on register bank

l   Peripherals

n   Up to 32 GPIOs for QFN48L

n   1 CAN controller support CAN2.0B and CAN FD

n   2 hardware UARTs

n   2 hardware USARTs(UART&ISO7816-3 comb) with VCC support (up to 10mA)

n   3 SPI (Master and Slave)

n   4 Timers (2 32-bit and 2 16-bit)

n   1 24-bit SysTick Timer

n   1 WDT

n   1 RTC

n   1 PWM

l   Security co-processor

n   DES/3DES

n   SM4

l   Wakeup

n   13 IO wakeup sources for QFN48L

n   Up to 3 internal wakeup sources

u  DSRC wakeup

u  WDT

u  RTC wakeup

l   Auxiliary Functions

n   CRC16

n   TRNG

n   10 bits SAR ADC@ 100KSPS (4 ex CH, VDD, VBAT and Temperature Sensor)

n   Internal LDOs

l   Package

n   QFN48L (6x6x0.75-e0.40)

l  ETC CPC/OBU,

l   RFID,

l   远程无线控制系统,

l  物联网智能终端